1. Field of the Invention
The present invention relates generally to a method for modeling signal timing in custom circuit blocks for microprocessors.
2. Description of the Related Art
With increasing demand for more complexity and higher throughput from integrated circuits (IC's), there is an increased need for designers to completely understand the timing characteristics of the circuitry being designed into the IC and how that timing affects other subcircuits being designed into the IC. Further, because of shorter product life cycles, there is an increasing desire to have a product enter the marketplace quickly.
ICs vary in their level of complexity depending upon the operations they are designed to perform. Complex ICs, e.g., microprocessors, are typically built up using a plurality of circuit blocks, each designed to perform a subset of the tasks performed by the entire IC. Each block has design characteristics that are not only critical to its own operation, but also to the operation of the entire IC. The timing of operations performed within each block and the delay times for a signal moving from one block to another block are critical and must be carefully considered during the design phase so that information required by any given block is made available by a preceding block, prior to any operation requiring that information being initiated.
By analyzing timing information for each block and for each interconnect connecting various circuit blocks together, any critical paths caused by a particular design of an IC may be determined. A critical path is a path having a first block preceding a second block in a data flow, the second block depending on data provided from the first block, wherein that data is not provided by the first block in a timely manner. After determining if critical paths exist in a given design, designers can make design improvements to ensure that the design will operate as planned, such as by maximizing the speed with which operations in the first block are performed.
Each time it is necessary to determine the timing of signals within an IC, data relating to the design of the individual circuits within the IC are analyzed, such as input capacitance, delay arc, driver characteristics, and net list. Typically one timing model for each block is prepared, together with layout files which contain connectivity information as to how each block is linked to each other block, and other information regarding the delays associated with transmitting information along a given interconnect from one block to another. These files are then provided as input data to a timing analyzer which, using constraints for that particular design, determines whether all blocks will function according to the design parameters set forth by the designers. The output of the timing analyzer includes the identification of any critical paths that must be fixed in order for the IC to function properly.
Thus, the importance of accurately modeling the timing characteristics of each circuit block within the IC is evident. Conventional timing models for circuit blocks generally include the items listed in Table 1.
TABLE 1Conventional Timing Modeling Scheme1.Input pin name and capacitance2.Output pin name3.Input pin's setup/hold timeSCLK—in, HCLK—in4.Output pin's output delay DCLK—in5.Output pin's output resistance
Each of these items provide timing information that characterizes the performance of the particular circuit block. While the terms “input pin” and “output pin” are used, it should be recognized that these do not necessarily refer to actual physical pins, but are merely points of entry or exit to for the custom circuit block. The input and output pins will generally be connected to other circuit blocks or input/output interfaces within the integrated circuit. It should be noted that the input pin's setup and hold time SCLK—in, HCLK—in and the output pin's output delay time DCLK—in values are determined with reference to the clock input signal, i.e., the amount of time in advance of and behind of the clock input signal necessary to provide for setup and hold. And the amount of delay time from the clock input signal to the output pin.
Circuitry within a circuit block can often be segmented between main circuitry and timing circuitry. The main circuitry performs the desired function of the circuit block, i.e., memory read/write, arithmetic, or other processing task. The timing circuit generally includes a clock buffer tree that receives an external clock signal and provides multiple clock signals as necessary to the main circuit. Clock signal lines passing from the timing circuit to the main circuit pass through what will be referred to herein as the clock reference point (CRP).
The input pin's setup/hold time and the output delay of the output pin may be determined by simulating the particular circuit block as a whole. This measures a signal delay from the clock input pin, through the CRP, to the signal output pin. For the setup/hold time, the timing difference between the clock input pin and the input signal pin is measured. Such simulations are based on computerized models of the circuitry within the circuit block. However, the criticality of the timing circuitry requires that it be very accurately modeled. Thus, building a schematic including of the timing circuitry can be laborious and time consuming. Furthermore, because of the complexity of the timing circuit, the simulation tends to take a great deal of time to run. This contrasts to the main circuitry, which tends to be repetitive, in the case of blocks providing memory functionality, or is otherwise simpler to model and simulate. Each time the clock circuit or main circuit is updated, the timing characterization for the entire block must be recalculated based on a new simulation for the modified block.
To reduce the complexity of modeling and simulating the clock circuitry, circuit blocks have also been modeled based on the worst-case specification number for timing of the entire IC to determine the clock signal delay of just the timing circuitry for the particular circuit block. Thus, in this case, the delay from the CRP to the input/output pins is estimated without real clock information. This allows the main circuit to be modeled from the CRP to the output pins, and the delay associated therewith to be simply added to the worst-case specification number. Clock buffer delay analysis is performed to assure that the clock delay from the clock input pin to the CRP meets the defined clock specification, and then for the timing analysis, the defined clock specification is used.
Since the worst case clock specification is used rather than one specific to the particular circuit block being modeled, the input pin's setup/hold time and the output delay estimates may be too conservative. This places an extra burden on designers to reduce the delay of the main logic circuit, which requires additional and possibly unnecessary engineering design time.
The known methods for assessing the timing parameters of custom circuit blocks has therefore not adequately addressed the need to provide accurate results in a timely manner.